The arrival on the market of components operating at high frequency (memories, processors, etc.) means that the use of unencapsulated chips (bare chips) poses novel problems of efficiency. The testing of bare chips using probe tips becomes very tricky beyond frequencies of about 1 GHz. The prime consequence is that in the case where these components are stacked in a 3D electronic module, certain chips will be able to operate at the maximum frequency, others will not; it follows from this that a module comprising a plurality of chips will not be able to operate at the maximum frequency.
A means of circumventing this difficulty is to use encapsulated chips, that is to say ones placed in a package which can, itself, be fully tested. Indeed, a package comprises outputs in the form of solder balls which are at greater spacings than that of the pads of the chips:                Spacing of the pads of the chips: 50 to 100 μm,        Spacing of the ball grid packages encapsulating a chip: from 400 to 800 μm.        
Test sockets can therefore be used and the packages are thus testable at frequencies of possibly greater than 1 GHz, as well as at operating temperatures lying between −55° C. and +125° C.
But a stack of packages is thicker than a stack of chips, and therefore leads to a likewise thicker 3D module whereas it is desired to obtain a 3D module with reduced thickness.
Starting from this observation, it is then necessary to find a stacking technology suitable for these packages able to operate at high frequency, and making it possible to obtain 3D modules with reduced thickness.
Consequently, there remains to this day a need for a method of collective fabrication of 3D electronic modules which is simultaneously satisfactory in respect of all the aforementioned requirements, in terms of reliability of the electronic chips at operating frequencies in particular greater than 1 GHz, at operating temperatures lying between −55° C. and +125° C. and of reduced thickness of the 3D modules obtained.
More precisely the subject of the invention is a method of collective fabrication of 3D electronic modules, each 3D electronic module comprising a stack of at least two, surface transferable, ball grid electronic packages, tested at their operating temperature and frequency, which comprises:
a step of fabricating reconstituted wafers, each reconstituted wafer being fabricated according to a first embodiment according to the following sub-steps in the following order:                A1) the electronic packages are placed on a first sticky skin, balls side,        B1) molding of the electronic packages in the resin and polymerization of the resin, to obtain the intermediate wafer,        C1) thinning of the intermediate wafer on the face of the intermediate wafer opposite to the balls,        D1) removal of the first sticky skin and placing of the intermediate wafer on a second sticky skin, side opposite to the balls,        E1) thinning of the intermediate wafer on the balls side face,        F1) formation of a balls side redistribution layer,        G1) removal of the second sticky skin to obtain a reconstituted wafer of smaller thickness than the original thickness of the electronic packages,        
several reconstituted wafers having been obtained on completion of the previous sub-steps, stacking of the reconstituted wafers,
dicing of the stacked reconstituted wafers to obtain 3D modules.